1. Field of the Invention
The present invention relates to a design data creating method of correcting a position of a contact hole layer pattern when creating design data of a semiconductor device, a design data creating program product, and a manufacturing method of a semiconductor device.
2. Description of the Related Art
With miniaturization of a semiconductor device, a defect in electrical characteristics due to an interlayer matching displacement or a finished dimensional error has been a serious problem. For example, when an interlayer overlay of a metal wiring layer and a contact hole layer is displaced, a sufficient contact area cannot be assured. As a result, a contact resistance between layers is increased, RC delay occurs, and a signal timing becomes inconsistent. In addition, even when a finished shape of a metal wiring on a wafer becomes smaller than a designed shape because of an error in manufacturing processes, the contact resistance is increased.
FIGS. 7A and 7B are plan views showing interlayer design restrictions of a metal wiring layer and a contact hole layer. FIG. 7A is a view showing an example where the design restrictions are satisfied, and FIG. 7B is a view showing an example where the design restrictions are not met. In order to avoid an increase in contact resistance due to a reduction in contact area, on a design stage in a conventional technology, as shown in FIG. 7A, design restrictions are set to provide a margin between a metal wiring layer M and a contact hole layer V. Adopting this structure enables acquiring a specified contact resistance even if an interlayer matching displacement or a finished dimensional error is present.
In a conventional design data creating method of a semiconductor device, pattern shapes of a metal wiring layer and a contact hole layer are first determined by using a regular placement and routing tool. Then, in order to increase a manufacturing process margin of the metal wiring layer, processing of increasing a width of a metal wiring line at a position where the pattern is narrow, i.e., so-called widening processing is carried out. Therefore, a pattern of the metal wiring determined by the placement and routing tool is different from an actual pattern of the same obtained after the widening processing. It is to be noted that the contact hole layer is still arranged by using the placement and routing tool, and it is arranged based on design data before the widening processing for the metal wiring line is carried out.
FIGS. 8A, 8B, and 8C are views showing a conventional design data creating method of a semiconductor device. FIG. 8A is a view showing a pattern shape obtained after placement and routing, FIG. 8B is a view showing a pattern shape obtained after the widening processing, and FIG. 8C is a view showing a pattern shape obtained based on a simulation. In a provisional pattern layout obtained after placement and routing depicted in FIG. 8A, a contact hole layer V is symmetrically arranged widthways with respect to a corresponding metal wiring layer M. However, in the pattern shape after the widening processing depicted in FIG. 8B, the contact hole layer V is asymmetrically arranged (biased to the left). Therefore, a contact area of the metal wiring layer M and the contact hole layer V may not be sufficiently assured due to an interlayer mating displacement of metal wiring layer M and the contact hole layer V or a finished shape error caused by a manufacturing process.
FIG. 8C shows shapes of the metal wiring layer M and the contact hole layer V on a wafer when a simulation is carried out based on a pattern layout obtained after the widening processing. After the widening processing, it can be understood that V protrudes from a region of M due to shortening of an end side of M and a contact area of M and V is reduced in the simulation even though an interlayer matching displacement does not occur. That is, in such a pattern layout, a high process yield cannot be obtained in manufacture of a semiconductor device.
It is to be noted that Jpn. Pat. Appln. KOKAI Publication No. 2002-131882 discloses a method of extracting a pattern whose process margin with respect to fluctuations in an exposure amount and a focal distance does not reach a predetermined reference value from a design pattern of a mask that is used at a light exposure step of a semiconductor device designed in accordance with a predetermined design rule, and correcting the pattern in such a manner that the process margin satisfies the reference value.